Incorrect timing diagram in Texas Instruments ADS7883 datasheet

There seem to be errors in figure 21 of the datasheet for the ADS7883 ADC.

Figure 21 from ADS7883 datasheet

Datasheet figure 21 depicts, that SDO is high impedant until the first falling edge of SCLK, then zero (i.e. low) and another zero is transmitted at the next rising edge of SCLK. All following bits are depicted to be transmitted at rising edge if SCLK.

This is not what can be observed when talking to the chip, though.

Transaction between an SPI master and an ADS7883 (please excuse the poor signal quality).
Red: nCS, yellow: SCLK, blue: DATA from ADS7883.

From the measured SPI transaction it can be seen, that data is actually clocked out at the falling rather than the rising edge of SCLK. The connected SPI master can therefore sample the data at the rising edge of SCLK. Also, one rather than two leading zeros are being transmitted by the ADS7883. Accordingly, the ADS7883’s output already returns to zero at the 13th falling edge of SCLK.

This update should be sufficient to realize a functioning implementation. If I have some spare time, I might contact Texas Instruments about it…

230 mal insgesamt angesehen, 1 mal heute angesehen.
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